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00:00:00 --- log: started osdev/18.01.16
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01:48:36 <gamozo> what what is L1OM?
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01:49:38 <gamozo> first gen xeon phi?
01:52:08 <bcos_> Sounds unlikely
01:52:20 <bcos_> Where did you see "L1OM"?
01:53:35 <gamozo> it is :\
01:53:37 <gamozo> sandpile opcode enc
01:53:44 <gamozo> "L1OM misc and L1OM vector"
01:53:47 <gamozo> which is part of K1OM
01:53:51 <gamozo> which is xeon phi first gen
01:54:03 <moondeck[m]> https://software.intel.com/en-us/forums/intel-many-integrated-core/topic/536316
01:54:04 <geist> knights landing, i guess
01:54:08 <bslsk05> software.intel.com: How to disassemble with objdump for programs running on mic
01:54:17 <gamozo> knights corner was first gen
01:54:20 <gamozo> knights landing is EVEX
01:54:22 <geist> er that.
01:54:43 <gamozo> alright, so i don't need to support that, phew
01:54:44 <bcos_> Wasn't there something in between larabee and knight's corner?
01:54:52 <gamozo> not sure
01:55:08 <gamozo> cause I thought KNC was MVEX, but maybe it was only partially MVEX
01:55:14 <bcos_> Ah - wikipedia - knight's ferry
01:55:15 <gamozo> but yeah, it could be something inbetween
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11:38:45 <kimundi> Hi! As part of a university course I'm writing a small x86_64 OS. As part of a extension, I want to enable floating point support in it, but the provided code framework does not have any support enabled for it per default - which means I get a illigal instruction interrupt as soon as I just define a floating point variable
11:39:32 <kimundi> I've tried looking at the osdev wiki of what is involved, but I could not yet find clear concise instructions
11:41:02 <bcos> "floating point" is either the FPU, SSE, or AVX; where each different extension is enabled differently
11:41:12 <kimundi> As far as I know, I need help with 1) enabling all relevant hardware support in the startup assembler file 2) saving the correct floating point registers during an interrupt 3) saving the correct floating point registers during a context switch (2 and 3 are independent mechanisms in this codebase)
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11:42:57 <kimundi> bcos: Either would be fine with me, I don't need fancy support for simd or stuff like that - I just want floats, the basic arithmetic operators, and a few special operations like sin/cos/sqrt
11:43:34 <kimundi> If there is a gcc compiler flag I can/should set to make it behave better, or just pick a simpler subset of the hardware support during codegen, that would help to know too :)
11:43:54 <doug16k> kimundi, all x86_64 operating systems use sse
11:43:57 <kimundi> I can provide links to my OS code/the startup assembler file if it help
11:45:20 <bcos> kimundi: Probably begin here: http://wiki.osdev.org/SSE#Adding_support
11:45:21 <bslsk05> wiki.osdev.org: SSE - OSDev Wiki
11:45:30 <bcos> ..then read the CPU's manuals :-)
11:45:32 <doug16k> see the intel manual, look up the control registers. CR4 has two bits that enable sse: OFXSR and OSXMMEX. if they aren't set, the CPU will treat all SSE instructions as invalid opcodes.
11:45:40 <kimundi> doug16k: Yeah, afaik its mandated per specification - but the code we have doesn't initialize it. I have added a bit of assembler from the osdev wiki for enabling sse, but I don't know if its correct
11:46:18 <doug16k> so save and restore state, you need to use at least fxstor and fxrstor, which saves the x87 FPU state and the 128-bit SSE registers
11:46:53 <kimundi> Yeah, that piece of code is what I added
11:48:00 <kimundi> https://github.com/Kimundi/oostubs-temp/blob/marvin-aufgabe-6/startup.asm#L426
11:48:02 <bslsk05> github.com: oostubs-temp/startup.asm at marvin-aufgabe-6 · Kimundi/oostubs-temp · GitHub
11:49:33 <doug16k> kimundi, that looks like it would work. can you show the fxsave/fxrstor code?
11:51:32 <doug16k> kimundi, do you realize that reading/writing the low 16 or 32 bits of a register truncates the high 32 bits?
11:51:40 <doug16k> you should use rax there, not ax
11:51:58 <doug16k> and extend that mask to 64 bits wide
11:52:24 <kimundi> doug16k: So, there are two different places where the code is saving registers - once for interrupts, and once for switching coroutines - I'll link both, afaik only one of those uses the fstore/fload instructions, and our tutor said that we shouldn't trust in it being correct
11:53:13 <kimundi> This is the interrupt handler: https://github.com/Kimundi/oostubs-temp/blob/marvin-aufgabe-6/startup.asm#L251
11:53:15 <bslsk05> github.com: oostubs-temp/startup.asm at marvin-aufgabe-6 · Kimundi/oostubs-temp · GitHub
11:53:21 <doug16k> the fxsave/fxrstor operand is required be 512-bit aligned
11:53:38 <bcos> Much better to make sure IRQs (and possible entire kernel) don't use SSE/AVX to avoid the massive cost of saving/loading their state very often
11:53:55 <kimundi> And this is the corotine context switch: https://github.com/Kimundi/oostubs-temp/blob/marvin-aufgabe-6/machine/toc.asm#L48
11:53:56 <bslsk05> github.com: oostubs-temp/toc.asm at marvin-aufgabe-6 · Kimundi/oostubs-temp · GitHub
11:54:24 <doug16k> those are old save/restore instructions. you should use fxsave/fxrstor
11:54:44 <doug16k> also, it won't work at all as shown
11:54:57 <kimundi> doug16k: > do you realize that reading/writing the low 16 or 32 bits of a register truncates the high 32 bits?: I'm barely comprehending what the assembler code is doing, its not really a focus of the course, so if there are any mistakes or weirdness, please tell me :)
11:55:01 <doug16k> oh wait, it might
11:55:39 <doug16k> on long mode x86_64, any time the destination of an instruction is an 8, 16, or 32 bit register, it truncates the high 32 bits to zero
11:55:59 <olsner> no, only 32-bit writes do that
11:56:07 <olsner> 8- and 16-bit accesses preserve the other bits
11:56:27 <kimundi> bcos: Hm true - we would only use the float stuff in a user process, so you think it would work if we don't touch the registers for interrupts, and only for context switches?
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11:57:06 <bcos> kimundi: That's how most OSs do it (except for special cases where SSE/AVX helps a lot)
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11:57:45 <kimundi> Our tutor also said it might work if we just have a single process do floating point calculation, since then it doesn't matter if context switching does not swap the registers out, but I'd like to at least know how to do it correctly
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11:58:03 <doug16k> kimundi, is "guardian" compiled code?
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11:58:23 <kimundi> yes, a C function that handles the interrupts
11:58:24 <kimundi> sec
11:58:40 <kimundi> https://github.com/Kimundi/oostubs-temp/blob/marvin-aufgabe-6/guard/guardian.cc
11:58:42 <bslsk05> github.com: oostubs-temp/guardian.cc at marvin-aufgabe-6 · Kimundi/oostubs-temp · GitHub
11:58:59 <doug16k> if you are going to skip saving/restoring sse state there, you need to make sure the compiler knows it can't touch the sse or fpu state
11:59:11 <kimundi> doug16k: Yeah, thats the tricky part
11:59:20 <kimundi> So I'd rather just store them correctly :)
12:00:27 <doug16k> the simplest way is to move rsp to a call preserved register (rbx,rbp,r12-r15) and sub rsp,512, then and rsp,-512 then fxsave [rsp]
12:00:37 <bcos> Might be useful to get "only single process uses floating point" working first (to make sure the initialisation works); and then add state save/restore to task switches after you know the initialisation works
12:01:11 <doug16k> then when that function returns, fxrstor [rsp] then mov that call preserved register to rsp, then continue with what you have
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12:02:34 <doug16k> the other way is to use -mgeneral-regs-only when compiling the c++ code, to ban it from touching sse/fpu
12:02:35 <b0l_> GDT is set before the SMP setup, if GDT is unique per system, how other cores know the gdt address on mem?
12:02:59 <doug16k> b0l_, you have to set up every cpu
12:03:25 <kimundi> doug16k: Hm, that flags sounds like a easy fix too - does that prevent me from doing floating point operations?
12:03:32 <doug16k> yes
12:03:33 <b0l_> so the same gdt is setup on all cores/cpus during the smp setup
12:03:52 <kimundi> doug16k: nvmd then :)
12:03:54 <doug16k> b0l_, usually the same, yes you must set up each cpu
12:04:01 <b0l_> ok
12:04:12 <b0l_> same for LDT?
12:04:31 <doug16k> b0l_, same for everything. the other cpus don't magically change because you set it for one cpu
12:04:47 <b0l_> eheh, right
12:05:03 <kimundi> doug16k: The context switching code uses this struct for holding the register state: https://github.com/Kimundi/oostubs-temp/blob/marvin-aufgabe-6/machine/toc.h
12:05:04 <bslsk05> github.com: oostubs-temp/toc.h at marvin-aufgabe-6 · Kimundi/oostubs-temp · GitHub
12:05:22 <doug16k> b0l_, GDT, LDT, IDT, all of the control registers, TSS, you name it.
12:05:33 <kimundi> doug16k: If understand you right, I should extend that last field to 512 bytes, and use the fx load/store instructions?
12:05:39 <doug16k> sorry, TR, not tss
12:05:49 <kimundi> DO I also need to somehow ensure the alignment fo 16 bytes there?
12:05:54 <b0l_> what is TR?
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12:07:37 <doug16k> kimundi, yes, it must be aligned on a 16 byte boundary, and the size of the fxsave data is 512 bytes
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12:08:04 <doug16k> oops, earlier I meant: sub rsp,512, then and rsp,-16 then fxsave [rsp]
12:08:28 <doug16k> oh but you aren't saving it on the stack, sorry
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12:08:45 <doug16k> you must set up that structure where you save the state so the fxsave area is 16 byte aligned
12:10:46 <doug16k> kimundi, yes, fxsave/fxrstor saves/restores the x87 state (old FPU) and the sse registers
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12:12:09 <doug16k> the registers, the mxcsr, the floating point control word, everything to do with fpu and sse
12:12:12 <kimundi> doug16k: Sorry, my connection dropped, "you must set up that structure where you save the state so the fxsave area is 16 byte aligned" is the first what got through again
12:12:35 <doug16k> <doug16k> kimundi, yes, fxsave/fxrstor saves/restores the x87 state (old FPU) and the sse registers
12:12:57 <doug16k> <doug16k> the registers, the mxcsr, the floating point control word, everything to do with fpu and sse
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12:13:47 <kimundi> Okay, thanks :) SO I guess I have to figure out how to make sure the filed of this struct is 16 byte aligned...
12:16:24 <doug16k> kimundi, if it is C++11 code, it is as easy as putting alignas(16) before the type
12:17:06 <kimundi> doug16k: C++17 even - the issue is that assembler code wants to access it, and I'm not sure how to compute the correct aligned address then
12:17:15 <kimundi> Eg, there is this file: https://github.com/Kimundi/oostubs-temp/blob/marvin-aufgabe-6/machine/toc.inc
12:17:16 <doug16k> just get the rdi offset right and you're good
12:17:16 <bslsk05> github.com: oostubs-temp/toc.inc at marvin-aufgabe-6 · Kimundi/oostubs-temp · GitHub
12:17:59 <doug16k> put .align 16 before line 32 there
12:18:18 <kimundi> thanks!
12:19:24 <doug16k> b0l_, TR is the register that gets loaded when you ltr a TSS descriptor
12:20:10 <doug16k> b0l_, it holds the base and limit of the TSS
12:20:51 <doug16k> b0l_, usually each CPU needs a different TSS as well, since it doesn't make sense for multiple CPUs to share the same kernel stack
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12:21:55 <kimundi> doug16k: In toc.inc I changed the line 32 to ".align 16 fpu_offset: resb 512", and I get "machine/toc.inc:32: error: parser: instruction expected" - maybe wrong assembler syntax? Its using nasm
12:22:25 <doug16k> oh nasm, sorry. I think it is [align 16] in nasm (I haven't used nasm in years)
12:23:04 <kimundi> "error: unrecognised directive [align]" - nope, not either - I'll google it know that I know what to look for
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12:23:22 <doug16k> just align, no []
12:23:33 <doug16k> ALIGN 16
12:23:42 <doug16k> http://www.nasm.us/xdoc/2.13.02/html/nasmdoc4.html#section-4.11.12
12:23:43 <bslsk05> www.nasm.us: NASM - The Netwide Assembler
12:24:20 <kimundi> "error: attempt to assemble code in [ABSOLUTE] space"
12:24:21 <kimundi> hmmm
12:25:49 <doug16k> ah crap, then you'll probably need to directly adjust $
12:27:11 <lava> any quick idea why i could be not getting pagefaults on a kernel page when running in kernel mode despite setting it to read-only and writing to it?
12:27:18 <lava> i would expect a write pagefault
12:27:32 <doug16k> lava, did you invlpg it?
12:27:34 <bcos> kimundi: Use "alignb" in the .bss and absolute sections
12:27:53 <lava> doug16k: should swap cr3 suffice?
12:28:06 <doug16k> lava, not if the PTE has global bit set
12:28:12 <lava> no global bit set
12:28:23 <doug16k> did you enable CR0.WP ?
12:28:35 <kimundi> bcos: alignb seems to be accepted,thanks!
12:28:38 <bcos> lava: There's a "WP" flag in CR0 that you'd need to set - without that the CPU ignores "read-only" for supervisor
12:28:43 <lava> ah!
12:28:47 <lava> that must be it
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12:31:56 <kimundi> doug16k: Hm, the C++ side does not seem to like a alignas(16) before the fpu member either - loking at cppref, it seems like its supposed to go on a struct itself?
12:32:48 <doug16k> works for me
12:32:58 <b0l_> pagefault in kernel mode should happen with PAE I guess
12:33:00 <kimundi> alignas(16) char fpu[512];
12:33:17 <kimundi> error: expected specifier-qualifier-list before ‘alignas’
12:33:17 <doug16k> yeah, that should work. what does the compiler say?
12:33:29 <kimundi> ah wiat, I think this one file compiles as C instead of C++
12:33:42 <kimundi> For reasons I could not comprehend
12:34:11 <doug16k> ok, then manually add padding
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12:34:28 <doug16k> figure out the offset of it and put a dummy char array before that member
12:34:44 <doug16k> or, reorganize it so it is the first member and registers are after
12:34:49 <lava> many thanks from my students
12:34:51 <kimundi> is that all alignas does? add padding? how does that ensure the final address of the member is at a 16 byte boundary?
12:34:56 <doug16k> first way is probably easier
12:35:04 <lava> they're implementing copy on write for some kernel pages
12:35:15 <lava> (page tables and such)
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12:35:25 <doug16k> kimundi, it will propagate to the enclosing type, so that whole structure takes on the largest alignment of its members
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12:35:57 <kimundi> doug16k: that seems to imply to me that it doesn't do that with manual padding though, only with an explicit alignas, right?
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12:36:11 <doug16k> it doesn't with manual padding, correct
12:36:20 <doug16k> that's why alignas is good :)
12:36:31 <kimundi> okay - then I'll just goolge what gcc extension I can use for C code here :P
12:36:51 <doug16k> if it is gcc, use __attribute__((aligned(16)))
12:37:02 <kimundi> after the member?
12:37:29 <doug16k> before the type should work
12:37:31 <kimundi> alright, seems to work
12:38:07 <kimundi> https://gcc.gnu.org/onlinedocs/gcc-3.2/gcc/Variable-Attributes.html - nope, after
12:38:08 <bslsk05> gcc.gnu.org: Using the GNU Compiler Collection (GCC)
12:38:17 <doug16k> dude, I just tried it
12:38:42 <doug16k> but sure, do what docs say
12:39:05 <sortie> kimundi: That is ancient gcc documentation. gcc 3.2 is ancient.
12:39:19 <kimundi> Sorry! Just tried it as well after the type and wanted to make sure there is no misunderstanding
12:39:24 <sortie> You want to read https://gcc.gnu.org/onlinedocs/gcc/Variable-Attributes.html :)
12:39:25 <bslsk05> gcc.gnu.org: Using the GNU Compiler Collection (GCC): Variable Attributes
12:39:51 <sortie> (Not that you did anything wrong -- I'm just helpfully directing people to the latest documentation whenever I see old links -- sometimes search engines gives you old versions that you shouldn't read)
12:40:00 <bcos> "university project" - probably stuck with the old version
12:40:34 <doug16k> putting it at the end of the line is disgusting imho, but whatever works
12:40:42 <kimundi> sortie: Yeah, its old gcc, but I would have been surprised if this particular syntax would have changed in a subtle way after I saw it :)
12:40:50 <sortie> bcos: Ah yes. I remember OS class that was stuck on a gcc 2.99. I managed to bootstrap a gcc 4.x on a Linux 2.2 system so it wasn't horrible.
12:41:13 <sortie> kimundi: Ah I missed the old gcc requirement :) Just pattern matching on limited context. :)
12:41:37 <kimundi> doug16k: I was not sure if putting it before might accidentally make it aplly to the member before it
12:41:49 <doug16k> through the semicolon?
12:41:56 <bcos> I think that sort of thing happens a lot - professor slaps together "resources" and then re-uses it for about 2 decades.. ;-)
12:42:42 <kimundi> doug16k: Just before you would not expect this, does not mean it couldn't happen! ;)
12:42:49 <kimundi> because*
12:43:23 <kimundi> anyway, thanks again you two - I've add everything to the code, and the OS seems to still run correctly
12:43:48 <doug16k> nice
12:44:14 <kimundi> bcos: Yeah - its interesting in this case because the prof upgraded to making this course about a _x64 OS for the first time this semester
12:44:16 <doug16k> note that that won't work for avx. I doubt the course requires avx support
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12:44:38 <doug16k> avx = 256 bit sse registers
12:45:10 <kimundi> doug16k: Depends on what the compiler spits out, I guess
12:45:15 <doug16k> to enable that you need 512 bit aligned context save area, and to use xsetbv to configure xsave/xrstor
12:45:22 <doug16k> it won't spit out avx unless you tell it to
12:45:24 <kimundi> good to know
12:45:40 <kimundi> even with optimizations enabled? (but not march=native) ?
12:45:48 <kimundi> just asking what to expect
12:46:17 <doug16k> only newer processors have avx. you should expect it to stick to 128-bit registers, which fxsave/fxrstor will support
12:46:23 <kimundi> alright
12:46:36 <doug16k> march=native will probably enable avx on a newer machine though, be careful with that
12:48:16 <doug16k> you can force avx off with -mno-avx
12:48:46 <doug16k> so -march=native -mno-avx will probably work with what you have
12:49:43 <kimundi> I'll add the -mno-avx to be sure then
12:49:54 <kimundi> Okay, so this is the full diff: https://github.com/Kimundi/oostubs-temp/commit/208665c44b66f33d6609cffc1fb483b1e1f59e8d
12:49:56 <bslsk05> github.com: enable sse, and do proper sse state saving · Kimundi/oostubs-temp@208665c · GitHub
12:50:02 <kimundi> Does this look correct?
12:50:30 <doug16k> looks right
12:50:43 <doug16k> did you set those CR4 bits?
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12:52:08 <kimundi> doug16k: err, not sure: https://github.com/Kimundi/oostubs-temp/blob/marvin-aufgabe-5/startup.asm#L426
12:52:09 <bslsk05> github.com: oostubs-temp/startup.asm at marvin-aufgabe-5 · Kimundi/oostubs-temp · GitHub
12:52:19 <kimundi> If that code is correct?
12:52:23 <doug16k> yeah -> https://github.com/Kimundi/oostubs-temp/blob/marvin-aufgabe-5/startup.asm#L432
12:52:25 <bslsk05> github.com: oostubs-temp/startup.asm at marvin-aufgabe-5 · Kimundi/oostubs-temp · GitHub
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12:52:54 <kimundi> Ah, was I supposed to change that to eax or rax or so?
12:53:09 <doug16k> no it's fine
12:53:15 <kimundi> kay, thanks
12:53:30 <doug16k> I was wrong earlier, only 32 bit writes zero upper 32. thanks olsner
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12:55:11 <doug16k> "32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination general-purpose register." "8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56 bits or 48 bits (respectively) of the destination general-purpose register are not modified by the operation."
12:56:22 <doug16k> it's not great for performance to make the CPU merge the partial register, but for that one time thing, a nanosecond is irrelevant
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12:56:30 <kimundi> yeah
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13:13:33 <b0l_> why cr0.WP is useful for process CoW? the WP bit doesn't affect only kernel bahaviour?
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13:19:57 <lava> b0l_: well
13:20:18 <lava> imagine you map the page tables to kernel accessible virtual pages, but read only
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13:20:26 <lava> then you can implement copy on write for the page tables
13:20:36 <lava> so you only have to copy pml4, but nothing below
13:20:41 <lava> anything below is copy on write
13:20:57 <lava> so... indirectly it is useful for process cow
13:21:16 <b0l_> what do you mean with "page tables to kernel accessible virtual pages"?
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13:21:56 <lava> you map the physical page table pages somewhere in the virtual address space in the process
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13:22:01 <lava> but not user accessible of course
13:22:06 <lava> + read only
13:22:26 <lava> then you need cr0.WP to actually enable the read only flag here
13:22:36 <lava> read only / writeable
13:22:55 <b0l_> ah ok
13:23:00 <b0l_> makes sense
13:23:17 <lava> so when you fork
13:23:22 <lava> you only need exactly 1 page
13:23:25 <lava> for the pml4
13:23:33 <lava> but no other page for the entire virtual address space
13:24:09 <b0l_> yes, because they are read-only and shared with parent
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13:33:38 <b0l_> lava: what I don't get is, if is the process to make the write, the CoW happens also if WP is 0, because the write is always deny from Userspace
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14:02:07 <b0l_> in which case the kernel triggers the CoW for a process page?
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14:06:04 <Belxjander> anyone here got any UEFI Linux kernel config recipes that are good baselines to start with
14:06:08 <Belxjander> ????
14:06:48 <Belxjander> I've been running into issues trying to configure a Linux kernel to actually bootstrap at all off a UEFI firmware (refind as bootloader with grub as alternate)
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14:09:09 <sortie> Belxjander: I don't know. Are you trying to make your own operating system or work with the Linux kernel? If you are trying to work with the Linux kernel, ##kernel might be a better place to ask your question.
14:11:21 <Belxjander> sortie: we;ll I am trying to get a working linux config on a ;ap@top before working with an own project to make a "Linux profile" for essential userland<->kernel bindings within a Virtual Environment setup of my own
14:11:58 <Belxjander> I've been hacking the config for about a month or so without any single booting kernel at all...
14:13:06 <Belxjander> and when using refind...and downloading and trying ArchLinux/Gentoo/... and other pre-made kernels...I only have success with those when I am "msdos-bios" mode launching them...not a single kernel has actually launched from UEFI-Shell or GPT-UEFI(refind) bootstrap at all...
14:13:25 <Belxjander> and I have checked the laptop to make sure "secure boot" is actually disabled
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14:28:33 <muotori> i'm following the xv6 MIT course on my spare time and in one of the files it has some inline assembly which for me fails to compile with bunch of "junk after expression" errors
14:29:01 <muotori> supposedly it's quite widely used system and I see no one else reporting same issue so I'm wondering if something could be wrong in my environment
14:29:36 <doug16k> muotori, old assemblers don't like U or L or LL suffixes on constants. that'd be my first guess
14:29:43 <doug16k> what version of binutils are you using?
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14:32:30 <muotori> doug16k: 2.28
14:32:38 <doug16k> it would help a lot to see an example inline assembly statement that has the error
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14:33:11 <muotori> https://github.com/LYP951018/xv6/blob/master/lab/user/faultregs.c the errors start at line 106
14:33:12 <bslsk05> github.com: xv6/faultregs.c at master · LYP951018/xv6 · GitHub
14:33:17 <doug16k> 2.28 is new enough
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14:33:41 <muotori> user/faultregs.c:106: Error: junk `(%ebx)+0x24' after expression
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14:33:54 <muotori> these are the type of errors I get
14:34:44 <doug16k> because that is not valid syntax
14:34:52 <doug16k> should be 0x24(%ebx)
14:36:00 <doug16k> but double up the % inside an asm with constraints, so 0x24(%%ebx) in the asm statement
14:36:31 <b0l_> ah ok, a CoW can be triggered from kernel only with a syscall
14:37:47 <b0l_> read(fd, buf_ro, size) so cr0.WP is usefull when buf_ro is still read-only after a fork() and kernel (via read()) tries to write it
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14:39:42 <doug16k> muotori, there are better ways to inject constants into asm code than what that thing does with preprocessor tricks. you can use constraint inputs to pass in constants, give them names, and put them in the code with %n[some_name_here]
14:39:55 <muotori> doug16k: okay thanks, as that syntax is not in the inline assembly itself how would I go fixing those statements?
14:40:43 <doug16k> because it is doing it wrong. you have no way of knowing what "m" will end up being
14:41:46 <doug16k> it could end up being (%ebx) or worse, something that has an offset already. then you don't know whether to put + after the offset or not
14:42:44 <muotori> Okay, I see
14:43:03 <doug16k> I would change "m" (before), "m" (after) to [before] "r" (&before), [after] "r" (&after), then construct my operand like 0x24(%[before]) or after or whatever
14:45:04 <doug16k> with "m" you're saying "hey generate mystery instruction operand that accesses it somehow, kthx"... with "r" you're saying "give me the address in a register and I'll take over from there"
14:45:29 <doug16k> note that I also asked for the address using &
14:46:07 <muotori> doug16k: aha, cool. I'll try that out. Thanks for the suggestion!
14:46:26 <doug16k> this is one of the issues with gcc inline asm. it can be done wrong and still work. someday when the code generator does something different, boom, it's invalid
14:47:23 <doug16k> it worked because due to fluke, it happened to be something where +0x24 made sense. it doesn't make sense against (%ebx)
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14:47:38 <muotori> I see, yeah that makes sense
14:51:20 <muotori> It's gonna take me a bit instill all this, thanks for pointing me to right direction doug16k!
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16:06:13 <doug16k> it's a good idea to have WP on in the kernel even if you don't need it for CoW. without it, you could overwrite read only .text/.rodata/etc with crap
16:13:05 <doug16k> finally found and ordered 4x16GB (64GB) of DDR4-2400 ECC RAM. $961 all together \o/
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16:14:20 <Mutabah> Yeah, defensive WP is a very good idea
16:15:29 <pounce> One of the first things I did in my kernel :p
16:15:47 <pounce> makes accidently overflowing the stack a lot harder
16:16:44 <doug16k> I put a massive 4MB guard region around all my stacks :D
16:17:08 <doug16k> at both ends!
16:17:26 <pounce> I really ought to create a virtual memory manager
16:17:35 <pounce> right now my stack allocator is pitiful
16:17:57 <pounce> (no deallocation, static size, etc)
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16:22:44 <doug16k> pounce, implementing a virtual memory manager is fun, do it!
16:22:55 <clever> doug16k: also of note, if you try to dynamically allocate something over 4mb on the stack, it can still skip over that guard, gcc has some special flags, to make it poke around within the region its allocating, so it cant skip the guard
16:23:13 <doug16k> I have stack check enabled
16:23:20 <clever> nice
16:23:45 <doug16k> -fstack-check to be exact
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16:24:21 <doug16k> it generates `or $0,-xxx(%rsp)` in functions that use a non-trivial amount of stack space
16:25:55 <doug16k> most of my functions are pretty gentle on the stack so it doesn't always get emitted
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16:26:32 <pounce> doug16k: that's the plan, but I want to do scheduling first
16:26:47 <doug16k> my kernel's heap malloc and free are blazing fast so I don't have to avoid them like the plague
16:27:13 <pounce> what algorithm do you use for it? is it threaded?
16:27:30 <pounce> (and by that I mean does it support threads)
16:27:35 <doug16k> yes
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16:28:08 <doug16k> https://github.com/doug65536/dgos/blob/master/kernel/lib/heap.cc
16:28:10 <bslsk05> github.com: dgos/heap.cc at master · doug65536/dgos · GitHub
16:28:17 <doug16k> power of two bucket pools
16:29:06 <doug16k> you can create private heaps too
16:29:25 <doug16k> malloc/realloc/free are wired up to use a default one
16:31:19 <doug16k> anything over 64KB falls back to paged allocator, which is also very fast
16:31:45 <doug16k> I put a lot of effort into making the memory manager as fast as possible
16:32:29 <pounce> Yep, that's something else I need to rewrite
16:32:41 <doug16k> the common case in the heap allocator takes tens of nanoseconds. 47ns or so? I forget exactly
16:33:25 <pounce> how long have you been working on dgos?
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16:34:33 <doug16k> 1st commit 27 Oct 2016
16:34:57 <doug16k> there was a couple of month gap in there somewhere when I was swamped with other work
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20:22:36 <warnock> I'm attempting to create a program that runs on bare metal and it was working fine until I tryed to isolate things into functions. When I call a function it jumps to the address after the location of the call instead of the address of the called function. Does anybody have an idea why that might happen? https://gist.github.com/barryWarnock/0d63e414dbec77d64ec76c5977b7932a
20:22:37 <bslsk05> gist.github.com: broken real mode c program · GitHub
20:23:15 <warnock> see line 23 of decompiled_main.o
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20:25:33 <vdamewood> warnock: How are you linking it?
20:26:09 <warnock> ld -o tetris.bin -m elf_i386 -Ttext 0x1000 launch_tetris.o tetris.o --oformat binary
20:26:09 <warnock>
20:26:51 <warnock> ld -o main.bin -m elf_i386 -Ttext 0x1000 launch.o main.o --oformat binary
20:26:51 <warnock>
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20:28:23 <Mutabah> That looks like it hasn't been linked correctly... , wait is that the objdump of main.o or main.bin?
20:29:07 <warnock> main.o
20:29:25 <vdamewood> .o files won't have the correct locations in call instructions
20:29:27 <Mutabah> That's valid for main.o
20:30:10 <warnock> it's not calling a label though just a relative address which seems wrong
20:30:11 <Mutabah> (tip, link to a elf file, then use objcopy to convert it to a flat binary - makes it easier to debug)
20:30:22 <Mutabah> warnock: It's not showing the relocation information
20:30:44 <warnock> I'll try that, thanks
20:31:02 <vdamewood> warnock: When is .o file is made, there isn't enough information to locate a label's location at execution time.
20:31:44 <vdamewood> When is --> When a
20:32:18 <warnock> the reason I assumed that was the problem is that my code halts in qemu as soon as it hits a function call, I can do things before but not after
20:32:57 <vdamewood> How are you loading this thing, anyway?
20:34:12 <warnock> I copied boot.asm verbatim from this tutorial https://blog.ghaiklor.com/how-to-implement-a-second-stage-boot-loader-80e75ae4270c
20:34:14 <bslsk05> blog.ghaiklor.com: How to implement a second stage boot loader? – Eugene Obrezkov
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20:43:11 <Mutabah> warnock: Check the disassembly of the thing you actually run. And look into invoking a debugger in qemu (it has gdb support, which can be quite useful)
20:47:05 * geist is on a plane
20:47:10 <geist> entertain me
20:48:40 * Mutabah releases snakes
20:48:49 <vdamewood> geist: A statistician refused for months to fly a plane when he found out how likely it was that there was a bomb on any given flight. Then he found out what the odds were that there would be two bombs on any given flight. So, now he brings a bomb whenever he flies.
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20:50:56 <geist> vdamewood: hah
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20:51:37 <pounce> geist: where're you off to?
20:51:57 <vdamewood> An airport
20:52:37 <vdamewood> Most of my flights have ended up at airports.
20:53:15 <klange> mine tend to end in a body of water
20:53:29 <klange> my favorite part of flying is when you ride the yellow slide at the end
20:53:51 <vdamewood> They don't let you use that at the airport.
20:54:29 <asecretcat> yall haven't had a real flight until you've flown out of the atmosphere and into space
20:54:49 <vdamewood> I've only flown out of the atmosphere, not into space.
20:55:12 <vdamewood> I can't wait for a flight where I can do both.
20:55:40 <vdamewood> geist: So, did you pay the bajillion dollars for in-flight wifi?
20:56:44 <pounce> ^^DNS isn't blocked in flight, so one could possibly get internet access through DNS-packet metadata
20:56:53 <pounce> if they're crafty enough to set up their own DNS server
20:57:24 * vdamewood blinks
20:57:48 <klange> I have a thing for that.
20:58:01 <vdamewood> now I want to implement this.
20:58:09 <pounce> http://code.kryo.se/iodine/ vdamewood
20:58:10 <bslsk05> code.kryo.se: kryo.se: iodine (IP-over-DNS, IPv4 over DNS tunnel)
20:59:57 <klange> I have a custom thing that I tunnel ssh over
21:00:47 <vdamewood> pounce: Thanks.
21:01:25 <pounce> there's also http://savannah.nongnu.org/projects/nstx/ but it hasn't been updated in /15 years/
21:01:26 <bslsk05> savannah.nongnu.org: NSTX -- tunneling network-packets over DNS - Summary [Savannah]
21:03:08 <vdamewood> Now if only I had a Static IP address at home or a VPS.
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21:09:53 <geist> vdamewood, no i had a coupon
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21:10:26 <vdamewood> coupon redeemable for one free packet
21:12:10 <geist> that's basically my experience right about now
21:12:17 <geist> connection to my shell box keeps dropping
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21:33:41 <jjuran> The choice of MD5 seems questionable.
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