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Thursday, 3 May 2018

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04:20:42 <donch> ..
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04:26:30 <ljc> hey anyone know of any sys admin channels?
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04:30:26 <izabera> #bash ##networking ##linux #debian
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05:50:49 <FooBar__> "async FS api's won't help high iowait" is that true?
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05:54:19 <_mjg_> ENOCONTEXT
05:55:08 <FooBar__> What?
05:57:46 <FooBar__> _mjg_: was that for me?
05:58:25 <_mjg_> yes
05:59:04 <_mjg_> iowait wont drop, but you get the cpu time to do something else without creating more threads
06:00:07 <FooBar__> Do iowait specifically describes hardware storage/retrieval times?
06:01:41 <bcos> Depends on context - sometimes (if file sytems are the context) "iowait" is "request latency", sometimes (if scheduling is the context) "iowait" is time a task spends blocked
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06:01:57 <_mjg_> ye
06:02:26 <_mjg_> it wont help utilize the storage subsystem better. it will just let you not get blocked
06:02:38 <FooBar__> This is in reference to an application doing fs reads+wires
06:02:58 <bcos> For the latter; if you send an async request then spend 3 days processing data while you wait for the response and never block, then you've reduced iowait to zero
06:03:16 <_mjg_> so, what is the real context here
06:03:31 <FooBar__> bcos: yes that is my question
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07:06:30 <grange_c> Hello guys!
07:13:31 <bender> hello grange
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07:42:23 <jjuran> https://www.heise.de/ct/artikel/Exclusive-Spectre-NG-Multiple-new-Intel-CPU-flaws-revealed-several-serious-4040648.html
07:42:23 <bslsk05> ​www.heise.de: Exclusive: Spectre-NG - Multiple new Intel CPU flaws revealed, several serious | c't Magazin
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08:36:37 <izabera> dumb question: what does abm mean on linux in this line from /proc/cpuinfo? flags : fpu de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pse36 clflush mmx fxsr sse sse2 syscall nx lm nopl pni cx16 hypervisor lahf_lm abm
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08:59:28 <bender> https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)
08:59:29 <bslsk05> ​en.wikipedia.org: Bit Manipulation Instruction Sets - Wikipedia
09:01:16 <bender> it's a flag that tells you if you can have hardware-assisted bit manipulation routines from what i'm looking at
09:02:24 <bender> i guess programs could use it if they knew the target machine they're running on for speed?
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09:50:54 <izabera> i was confused because i've seen other machines with popcnt as a flag
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12:20:46 <doug16k> kvm fixed bmi instructions in TCG recently
12:20:53 <doug16k> er, qemu fixed*
12:21:20 <doug16k> they were throwing invalid opcode before
12:21:46 <doug16k> they were supposed to be implemented though, and cpuid had the flags set
12:25:42 <geist> grats
12:26:26 <geist> https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets oh those are kind of cute. i wonder if any compiler knows how to use em directly
12:26:26 <bslsk05> ​en.wikipedia.org: Bit Manipulation Instruction Sets - Wikipedia
12:27:02 <doug16k> gcc does
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12:27:45 <geist> via intrinsics or just general pattern matching?
12:27:58 <doug16k> general
12:28:01 <geist> neat
12:28:11 <geist> sadly they're new enough that i can't really use them in the kernel
12:28:13 <geist> but still nice
12:28:15 <doug16k> many of those are three-operand instructions
12:28:32 <doug16k> uses VEX encoding
12:28:39 <geist> ah
12:29:33 <geist> heh the alu needed to do pdep and pext is pretty big
12:29:53 <geist> i wonder if that runs these through the float alu, since there are already extract/pack stuff over there
12:31:06 <geist> though oy ucan imagine if you support the alu for doing these sort of extract/deposit, then you can reuse that machinery for a lot of other stuff
12:33:42 <doug16k> if you do compile with those, the biggest impact to codegen would be the availability of shlx/shrx/sarx - they don't require the shift to be in cl
12:34:21 <doug16k> in stuff like hash functions, not having to bottleneck stuff into cl repeatedly can be a win
12:34:48 <geist> popcnt is one i wish i had multiple times
12:34:55 <geist> but then i dont think arm has it so
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12:36:22 <geist> otoh a lot of bmi1 looks like things that arm64 has in their ISA already, especially bextr and whatnot
12:36:25 <geist> which is very handy
12:36:39 <geist> things that extract and insert runs of bits arm64 is fairly good at
12:36:42 <doug16k> lzcnt takes less cycles on some architectures too, oddly
12:37:06 <doug16k> less than bsr I mean
12:37:26 <geist> yeah that's odd. you would assume it would generate nearly the same uop
12:37:33 <doug16k> ya
12:37:50 <geist> but then maybe the odd flags stuff in it makes it harder to implement
12:38:35 <doug16k> ya
12:38:40 <geist> also TBM. RIP
12:38:44 <geist> never got to meetcha
12:38:55 <geist> wonder if any compiler ever got real friendly with that one
12:39:22 <geist> and/or if i -march=native code on a bulldozer what is the chance of hitting one of those and making the binary not portable
12:41:45 <geist> not that you should expect it to be portable, but in general you can usually rey on code compiled for an earlier version of the same cpu family to work on newer ones
12:41:55 <geist> well, same cpu vendor in this case
12:42:03 <doug16k> the worst downside is kvm's emulation is spotty. if your code accesses data that nested-page-faults then it might not be able to emulate it. upside is it catches non-volatile hardware accesses
12:43:19 <geist> http://palms.ee.princeton.edu/PALMSopen/hilewitz06FastBitCompression.pdf is interesting
12:44:47 <doug16k> neat. gives some implementation details of the instruction :)
12:45:07 <geist> yah
12:45:13 <geist> now whether or not they do it who knows
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12:45:29 <geist> there ws some reference that the bulldozer family does a bad job with their own TBM instructions, such that they're not really useful
12:45:50 <geist> https://stackoverflow.com/questions/47159807/do-intel-cpus-support-trailing-bit-manipulation-tbm-instructions someone talking about it in the comments
12:45:53 <bslsk05> ​stackoverflow.com: assembly - Do Intel CPUs support Trailing Bit Manipulation (TBM) instructions? - Stack Overflow
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12:46:37 <geist> the gist is that AMD at least in bulldozer family really biffed the pdep/pext, and did it the cheezy way. probably multi cycle. wonder what Agner says...
12:46:49 <geist> and wonder if they fixed it in Zen
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12:48:53 <geist> ah yeah, looking at agner's tables, the ryzen still does a bad job (6 cycles, 18 cycle latency)
12:49:04 <geist> vs all of the intel cpus since haswell (1,2)
12:49:09 <geist> including knights landing
12:51:51 <geist> so i guess AMD made a decision not to blow a lot of transistors on that one feature. implies that it is indeed quite expensive
12:52:20 <geist> seeing as it's 6/7 cycles on AMD, I'm guessing they implement the butterfy network across multiple cycles
12:53:10 <Brnocrist> so, it is true that Apple is thinking to move to ARM for mac?
12:54:53 <geist> why would any of us know that?
12:56:47 <Kazinsal> out of infinite universes, an infinite number of them will have an Apple that is moving to ARM for Mac
12:56:56 <Kazinsal> it is impossible to tell which universe we are in though
12:57:23 <Brnocrist> but there is one where itis possible!
12:57:23 <geist> personally i think it'd be neat, but i like ARM
12:57:42 <Kazinsal> but my magic 8 ball says "try again later"
12:57:58 <Kazinsal> so it's possible
12:59:38 <Kazinsal> meanwhile I'm sitting here hoping to hear about a zen based successor to the G-series embedded SoCs
13:00:13 <Kazinsal> Jaguar at low clock rates is getting long in the tooth
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13:20:59 <drakonis> Kazinsal, the rumour mill says that's happening soon
13:21:21 <Kazinsal> That'd be nice
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13:21:56 <Kazinsal> If that happens 2H 2018 then sometime 1H 2019 we might see DIY network appliance boards showing up with it
13:24:38 <drakonis> hmm, seems like they already announced the ryzen socs
13:25:01 <drakonis> https://www.amd.com/en/products/embedded-ryzen-v1000-series
13:25:02 <bslsk05> ​www.amd.com: AMD Ryzen™ Embedded Processors | AMD
13:26:23 <drakonis> this seems to be the replacement
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13:45:33 <lldd_> time to compile the cross compilers
13:46:00 <lldd_> (gcc 8.1)
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14:05:44 <sortie> lldd_: Yay
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14:17:33 <ebrasca> Hi I like to knowh some sugestion to learn about implementing raid.
14:20:05 <Ameisen> Trying to build a full GCC toolchain in msys2 is... odd
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14:42:37 <Ameisen> main issue seems to be that msys2 will define Windows drives as, say, /d/...... but those don't appear to be fully functional within the VFS
14:43:33 <Ameisen> a source file cannot have an #include with that path
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14:56:03 <Ameisen> this is causing a few issues with building the prerequisites for GCC since sometimes I have to pass a D:/ path, sometimes /D/, sometimes a relative path, depending on what the tools that are part of the build process can use
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15:01:57 <t3hn3rd> Evening all \o_
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15:11:21 * UNIVAC ​reports changes to wiki page "Building libgcc for mcmodel=kernel" by Rod: update tested compiler versions. <​https://wiki.osdev.org/index.php?title=Building_libgcc_for_mcmodel%3Dkernel&diff=22379&oldid=20974>
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15:29:55 <bender> UNIVAC: source
15:29:55 <UNIVAC> ​bender: Command not found: source
15:30:01 <bender> UNIVAC: help
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15:43:46 <ebrasca> Can someone recomend me some documentation to learn about raid?
16:00:31 <Mutabah> ebrasca: wikipedia?
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16:12:35 <ebrasca> Mutabah: In wikipedia are there some data on how to implement it?
16:17:22 <ebrasca> Mutabah: Thanks you.
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16:20:15 <bender> ebrasca: Welcome
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16:32:07 <Ameisen> was able to build the prerequisites. Now to try to build binutils/gcc/gdb
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16:36:26 <t3hn3rd> Anyone any idea why this would give such massive results? https://pastebin.com/7Y99YnN4
16:36:26 <bslsk05> ​pastebin.com: [Pascal] c:= 0; if CPUID.Capabilities0^.TSC then begin t1:= getDateTime; t2:= get - Pastebin.com
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16:38:29 <Mutabah> t3hn3rd: You missed kHz
16:38:37 <t3hn3rd> ...
16:38:44 * t3hn3rd quits life.
16:39:10 <Mutabah> :) No biggie, sometimes you just need a fresh view
16:39:48 <t3hn3rd> Definitely needed the fresh view! Had been looking at the code for the best part of an hour thinking "wut?"
16:39:52 <t3hn3rd> Cheers!
16:40:42 <_mjg_> everyone was there
16:41:02 <_mjg_> i was starring at a switch statement missing 'break'
16:41:18 <_mjg_> and did has trouble realising what is the problem
16:42:47 <t3hn3rd> I had the same brain-fart the other day when implementing Serial comms, turned out I had flipped the Port & Data params in my Serial.Send function call, so I was trying to send to some arbitrary port the data $3F8 repeatedly.
16:46:23 <t3hn3rd> Does this seem low for VirtualBox? https://i.gyazo.com/43832fb6b9ea811be6b5978ddc08e95a.png
16:46:54 <_mjg_> why vbox?
16:47:16 <_mjg_> fwiw with qemu you can pass an arbitrary subset of cpu flags
16:47:37 <t3hn3rd> I'm using both QEmu and VBox for testing :P
16:48:39 <t3hn3rd> I'd expect the Clock-Rate in QEmu to be low due to the fact that QEmu is running inside my virtualized dev environment, but VBox is running on my main system with Acceleration enabled.
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16:56:50 <t3hn3rd> Ahhh think I solved it actually, I forgot to take into account that the loop could have started half-way through a second passing on the RTC, so just added a loop before-hand to sync.
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17:11:07 <t3hn3rd> Right, am off to bed. Night all! \o_
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19:01:18 <bcos_> Grrr. "Spectre Next Generation" - 8 more vulnerabilities effecting Intel and some ARM CPUs:
19:01:20 <bcos_> https://www.heise.de/ct/artikel/Exclusive-Spectre-NG-Multiple-new-Intel-CPU-flaws-revealed-several-serious-4040648.html
19:01:20 <bslsk05> ​www.heise.de: Exclusive: Spectre-NG - Multiple new Intel CPU flaws revealed, several serious | c't Magazin
19:01:25 <klange> computers
19:01:26 <klange> were
19:01:26 <klange> a
19:01:27 <klange> mistake
19:02:28 <bcos_> 6502 isn't effected - time to port everything to 1980
19:02:52 <vdamewood> Does that mean my NES is safe?
19:03:07 <klange> someone wrote a rather awkward article about how C isn't a low level programming language because we're not all using super fast pdp-8s or something, and...
19:03:10 <klange> you know what...
19:03:13 <klange> maybe we should be
19:04:22 <klange> out of order execution and all this other stuff is gonna be the supersonic jets of computing - we dared go too fast, and it didn't work out, so now we'll backtrack
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19:06:19 <Mutabah> So, we'll get non-superscalar multicores instead?
19:06:34 <Mutabah> Got back to itanic maybe?
19:06:37 <bcos_> We won't backtrack. I suspect all the little buffers and caches will get tagged with extra information
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19:07:43 <Xark> klange: PDP-11. :)
19:08:00 <bcos_> (e.g. a "supervisor" flag for each cache line that causes "cache hit from user-space" to be treated as "cache miss")
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19:09:32 <Xark> bcos_: RISC-V people are playing around with an extension for 128 bit pointers where they have security bits in them (enforced by MMUish hardware).
19:10:16 <Xark> aka Tagged memory
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19:11:44 <bcos_> Xark: Sounds more like an alternative to paging
19:12:10 <bcos_> - the sort of thing that could be bypassed with speculative execution, etc
19:13:09 <Xark> bcos_: More like lower level access control. http://www.lowrisc.org/docs/tagged-memory-v0.1/tags/
19:13:10 <bslsk05> ​www.lowrisc.org: Tagged memory support · lowRISC
19:13:30 <Xark> I suspect "leaking info" is an implementation detail (that I do not think they will overlook).
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19:22:13 <Xark> I thought the "C is not a low level language" article was interesting (and true in some ways). However, the author didn't really have any great sounding suggestions as to what to do about it (something hand-wavey about a cluster of cores like a GPU...).
19:22:27 * Xark links Hacker News discussion (with article link at the top) https://news.ycombinator.com/item?id=16967675
19:22:37 <bslsk05> ​news.ycombinator.com: C Is Not a Low-Level Language | Hacker News
19:23:36 <Xark> (Based on some things the author says, asm isn't really low-level either... :) )
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19:31:06 <klange> Xark: That was my biggest problem with the article.
19:31:59 <klange> Making an argument about how C is still pretty "high level" because of caches or ooe or whatever is worthwhile.
19:32:15 <klange> But when we start diluting terms, what does that serve us?
19:34:24 <Ameisen> well, if caches and OOE make things high level... then assembly is high level
19:34:33 <klange> I've heard the old argument "but C was considered high level when it came about" and true as that may be, the bar has moved a /lot/.
19:35:04 <klange> Ameisen: Exactly - if that's where we're setting the bar, we've driven the entire concept of "high level" vs. "low level" into meaninglessness.
19:35:30 <klange> Machine code is high level!
19:38:20 <Xark> klange: Yep, agreed.
19:39:14 <Ameisen> If you aren't building the CPU yourself, you're just a script kiddie
19:39:39 <klange> If you didn't mine the ores yourself...
19:39:59 <bcos_> CPU is a black box that exposes a interface (e.g. 80x86 architecture). A language is relatively low level if it's relatively close to the CPU's interface. The trickery going on inside the CPU behind that interface (speculative execution, register renaming, ..) is completely irrelevant
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19:40:21 <klange> Hear hear.
19:40:22 <Ameisen> I may have mined the ores... but I didn't create the universe
19:40:55 <klange> Ameisen: Amateur. This isn't a place for your childish toying, computers are for real men. Now go home to your local galaxy cluster.
19:41:41 <klange> I bet you're a sentient blob of matter from some podunk planet like Urth.
19:42:04 <klange> It's not low level unless you're a hyperdimensional being like myself.
19:43:22 <Ameisen> hmm
19:43:28 <Ameisen> maybe that's where QEMU comes from
19:43:32 <Ameisen> Q
19:43:52 <klange> Fabrice Bellard is definitely a hyperdimensional being.
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19:55:15 <jjuran> Fabrice Bellard is a mouse??
19:56:42 <Mutabah> Well, on the internet, nobody knows if you're a hyperintelligent rodent
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